Massive Parallel Current Power Amplifier Concept for Power Hardware in the Loop Applications

Abstract

The development of the smartgrid increases the complexity of the current electric grid. To verify and validate the operation of the systems involved in it, Power Hardware-In-the- Loop (PHIL) technique allows to test the complete system in an exhaustive way. But the reduced bandwidth of the overall test system can cause inaccuracies and instabilities, which can be harmful for the Hardware Under Test (HUT) or the people who are performing the test. To increase PHIL performance and tackle these problems, this paper proposes a new concept of high bandwidth current amplifier. It is based on a topology of massive parallel interleaved buck-boost converter, which distribute in an equal manner the total current in all the branches. This current reduction allows to use transistors with better switching behaviour, which increase the bandwidth of the converter. Furthermore, a Discontinuous Conduction Mode (DCM) is used, obtaining the nominal output current in only one switching cycle. Description of the concept and the design parameters are provided. Finally, the behaviour of the proposed Power Amplifier (PA) at high frequency setpoint currents is shown in a Matlab/Simulink simulation.