Software phase lock loops for pulse width modulated rectifiers

Authors

  • Petr Simek Author
  • Jiri Skramlik Author
  • Josef Tlusty Author
  • Viktor Valouch Author
  • Ivo Pecha Author

DOI:

https://doi.org/10.24084/repqj08.253

Abstract

Simulation and experimental results of the use of

three SPLL (Software PLL) that differ by the method of the

detection of symmetrical grid voltage sequences (positive and

negative ones) in case of an unsymmetrical grid voltage system

with harmonics and under usual disturbances and parameter

changes of the grid are presented. The function of the DSC

(Delayed Signal Cancellation) based SPLL with

was experimentally verified under different grid voltage

disturbances with satisfactory results.

Author Biographies

  • Petr Simek

    Institute of Thermomechanics

    Academy of Sciences of the Czech Republic

    Prague, Czech Republic

    E-mail: simek@it.cas.cz

  • Jiri Skramlik

    Institute of Thermomechanics

    Academy of Sciences of the Czech Republic

    Prague, Czech Republic

    E-mail: skramlik@it.cas.cz

  • Josef Tlusty

    Department of Power Engineering

    Faculty of Electrical Engineering, CTU

    Prague, Czech Republic

    E-mail: tlusty@fel.cvut.cz

  • Viktor Valouch

    Institute of Thermomechanics

    Academy of Sciences of the Czech Republic

    Prague, Czech Republic

    E-mail: valouch@it.cas.cz

  • Ivo Pecha

    Elektro

    Bouzov, Czech Republic

    E-mail: ivo.pecha@seznam.cz

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Published

2024-01-24

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Section

Articles